How does antenna diode work

Thanks and regards. It will go through the diffusion. So while M3 is manufactured there's excess charge on it. But M4 and M5 aren't manufactured yet. So the piece of net on M3 which is having excess charge, isn't connected to the driver's output pin diffusion yet.

Hence there's no path for the charge to go into the diffusion. By the time M4 and M5 are manufactured, the charge on M3 is already grounded I don't know exactly how though , and there's no antenna violation anymore. Correct me if I am wrong somewhere. Thanks, Sagar. Now for such violations always prefer jumpers.

Hello, I have a question about the antenna rules All other layers will have antenna ratios as , etc But why only Top most layer has less ratio?? Hi experts could u plz explain detaildly regording antenna dide working. Thanks in advance.

Regards, Siddharth. Usually for Jumper you move to higher metal layer and then come down to lower metal Layer. In this scenario can Jump to Lower metal Layer and then again going back to Top metal layer will fix the Antenna Violation or we need to try something else. Nice explanation. No need refer anything else for understanding Antenna effect. Nice work!!!! I think you guys did an excellent job explaining the antenna effect. I will be looking forward to more information as a layout technician.

This will continue to help me emensely. Great Work!! Great explanation Could you expalin how to choose diode specifications or layout area for Antenna effect?

Yes, i too need some explanations regarding the operation of antenna diode. I just get artictle about tunnel diode , if you need to get more information about this electronic device check this. Hi A great article to understand antenna effect. Thanks for the detailed explanantion. I have one query regarding use of antenna diode. I have one doubt on diode insertion in reverse bias for antenna effect. Can you please explain the three sources of the stress voltage mentioned?

Hii, while calculating the maximum antenna ratio in the formula, i have seen a parameter called "Diode Protection" DP value, when diodes are used for preventing antenna violations.

Thank you very much for this post.. Hi, nice explanation for Antenna effect given. But i coundt get the Operation of the Antenna Diode, in this scenario. Hi, nice to read this, got idea what is antenna effect, causes and remedies but i didn't get the functionality of inserting diode i mean how it is operate. Provide reason for disabling antenna violations upto postroute stage by adding diodes.

Hi, Thanks a lot for such a nice explaination. I have a doubt. If there is an antenna violation in metal 1 means metal 1 has charge accumulated in it and to remove it, it is connected to M2 then again M1.

But Charge can still flow as all are metals connected to each other through via. So how this jumper is used as a remedy for antenna effect. Please reply. Would you mind if I share your blog with my twitter group? There's a lot of people that I think would really enjoy your content. Please let me know. Than you. And as there is no other functional use of nac diode.

So is there any possibility that antenna violation may come up in later stages of chips or the nac diode is just useless throughout the life of the chip after fixing the violation initially. Excellent article, I really appreciate it. One question. Are antenna diodes still suitable for usage in high-side circuits?

If the p-well is in an island surrounded by HVNW, will this have an impact on how effective the antenna diode will be?

Saturday, July 19, Antenna Effects. Apart from this, several unwanted things happen just because of several plasma processing steps.

One of them is the charging damage. Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOSFET during plasma processing.

The stress voltage that develops across the gate and substrate of a MOSFET during plasma processing basically comes from three sources.

You can expect a circuit with some redundant logic. What is Latch Up? How do you avoid Latch Up? Delay increases with load. It requires more time to cahrge high loads. Will it help the setup? The speed goes down with skew. When can we call selection line of multiplexer as a false path? How we will decide the path as a false path? Can you tell by taking mux as an example? Explain multi cycle path with example and waveform 2.

How is power consumption effected with shrinking technology? What are the different types of placements? How will u know whether to do a Timing Driven placement or Congestion Driven placement? What does timing library consist of? Look up tables? Explain setup and hold with example and waveforms. Que: Hot carrier effect? Que: Pass transistor concept?

Que: How buffer minimizes skew as gate delays is more than propagation or transition Delays? Que: Block diag. Of latch. How is it effected? Que: How to form cap in MOS? If Drain and source is shorted how will it behave Like a capacitor? Which type of cap is it? Que: Equation of VT? Que: How Mos device works? Cut-off, saturation, linear. Que: Equation of IDS in different region. Que: Electro migration Calculation Que: Antenna effect, from where the charge comes? Que: How layer hopping reduces the process Antenna effect?

Que: why distance between diffusion contacts? Que: cross section of MOS? Que: cut it in half; how the view looks like? Que: Guard Ring, secondary guard ring?

Why is it always as ring? Que: If u cut guard ring how will it look like? Que: Latch Up? Que: Antenna Effect? Que: In the following figure what will happen if u run the metal1 Power supply 20v over the poly. Que: What were the problems u faced while doing layout?

Que: Tell about following fig. What actually it is? Que: In diffusion region why multiple contact, what will happen if we put a big contact? How fingering effects the E. Positive Charge gets collected on the metal, from where this charge comes? Que: Explain Latch up? How the Vdd value will come down to 0. Que: When does the ESD occurs?

In processing or in operation? Que: when does the Electro migration occurs? In processing or in Operation? Que: How will u calculate the power stripe width? Que: How will u improve IR drop effect?

Que: RC ckt. MOS device cap curve? Value of C Substrate? Que: DFM rule? Que: How even no. How does it effect the quality of layout? Derive the maximum clock frequency for the circuit.

Derive the minimum hold time allowed for the circuit. What happens to delay if we include a resistance at the output of a CMOS circuit? What are the limitations in increasing the power supply to reduce delay? What happens if we increase the number of contacts or via from one metal layer to the next?

Explain its sizing a considering Vth b for equal rise and fall times. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus. I was given a 3 input AND gate and a 2 input Multiplexer.

Given a circuit, draw its exact timing response. What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? Hint: Double the Clock. Suppose you have a combinational circuit between two registers driven by a clock.

What will you do if the delay of the combinational circuit is greater than your clock signal? The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? Give the truth table for a Half Adder. Give a gate level implementation of the same. Now, how do you convert it to XNOR? Without inverting the output. How do you detect a sequence of "" arriving serially from a signal line?

These interview questions test the knowledge of x86 Intel architecture and microprocessor specifically. What is a Microprocessor? Most Micro Processor are single- chip devices.

Why processor is called an 8 bit processor? Similarly processor has 16 bit ALU. What does microprocessor speed depend on? Is the address bus unidirectional? Is the data bus is Bi-directional? Dry etching : In this, plasma or etchant gasses remove unwanted material. This reaction that take place which can be done by utilizing high kinetic energy of particle beam or chemical reaction. Plasma etching is an anisotropic or highly uniform and fair directionality. Antenna rules: Foundry provides the antenna rule file, which must be followed during the layout design.

In the antenna rules most common rule is Antenna Ratio same as shown in fig2. Antenna ratio is the ratio of metal area connected to the gate to the total area of gate. The antenna rule specifies the maximum tolerance for the ratio of a metal line area to the area of connected gates.

VLSI process starts from the substrate, device layer and then metal layers. The Etch process builds up the electrical charges on metal layers.

These charges cause a high voltage spike, which may damage the gates connected to the metals. Gate area is the multiplication of channel length and channel width. Antenna problem is due to Bottom area and parameter of the metal line. Via and contact also contributes to the antenna violations. There are three kinds of antenna violations in the design: Metal area antenna rule: The maximum limit to the ratio of the metal line area to the connected gates area.

Perimeter antenna rule: The maximum limit to the ratio of the metal line perimeter connected gates area. Via or contact area: The maximum limit to the ratio of the via or contact area to the connected gates area. Antenna Preventions: Techniques to fix the antenna violations as follows: Routing on Higher Metal Layer: Long metal can be taken to higher metal routing layer. This is known as metal jumping.

This metal jumping is usually done near to the load. This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated.

Why would there be a charge build up during manufacturing that can occur at the gates of these nmos and pmos 2. What polarity is this charge? What kind of diodes i. Is there any kind of detailed literature that I can read? Thank you very much!! Could you please explain to me why you need antenna didoes: 1. Click to expand Hi cellphone Whenever the metal area connecting the poly is wider, it forms an antenna and in effect there will be charge accumulation in this area.

If it is a negative charge that is accumulated, the n diode conducts and the charge is grounded and viceversa. Regards Swathi.

In such processes, the wafer is bombarded with ions in order to create the polysilicon and metal layers. These ions must find a path through the wafer to the substrate and active layers at the bottom. If there is a large area of poly or metal, and if it connects ONLY to gates of transistors not to source or drain or any other active material then these ions will travel through the transistors. If the ratio of the poly or metal layers to the area of the transistors is too large, the transistors will be destroyed due to a build up of charge.

Nothing to do with noise!